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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad6600 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 functional block diagram features dual if inputs, 70 mhzC250 mhz diversity or two independent if signals separate attenuation paths oversample rf channels 20 msps on a single carrier 10 msps/channel in diversity mode total signal range 90+ db 30 db from automatic gain-ranging (agc) 60 db from a/d converter range >100 db after processing gain digital outputs 11-bit adc word 3-bit rssi word 2 clock, a/b indicator single 5 v power supply output dvcc 3.3 v or 5 v 775 mw power dissipation applications communications receivers pcs/cellular base stations gsm, cdma, tdma wireless local loop, fixed access product description the ad6600 mixed-signal receiver chip directly samples signals at analog input fr equencies up to 250 mhz. the device includes two input channels, each with 1 ghz input amplifiers and 30 db of automatic gain-ranging circuitry. both channels are sampled with a 450 mhz track-and-hold followed by an 11-bit, 20 msps analog-to-digital converter. digital rssi outputs, an a/b channel indicator, a 2 clock output, references, and con- trol circuitry are all on-chip. digital output signals are two? complement, cmos-compatible and interface directly to 3.3 v or 5 v digital processing chips. the primary use for the dual analog input structure is sampling both antennas in a two-antenna diversity receiver. however, channels a and b may also be used to sample two independent if signals. diversity, or dual-channel mode, is limited to 10 msps per channel. in single-channel mode, the full clock rate of 20 msps may be applied to a single carrier. the ad6600 may be used as a stand-alone sampling chip, or it may be combined with the ad6620 digital receive signal pro- cessor. the ad6620 provides 10 db?5 db of additional pro- cessing gain before passing data to a fixed- or floating-point dsp. driving the ad6600 is simplified by using the ad6630 differen- tial if amplifier. the ad6630 is easily matched to inexpensive saw filters from 70 mhz to 250 mhz. designed specifically for cellular/pcs receivers, the ad6600 supports gsm, is-136, cdma and wireless lans, as well as proprietary air interfaces used in wll/fixed-access systems. units are available in plastic, surface-mount packages (44-lead lqfp) and specified over the industrial temperature range (?0 c to +85 c). dual channel, gain-ranging adc with rssi gain a/d converter timing encode select gain +12, +18db encode flt flt noise filter resonant port 630 rssi 3 two's complement 11 ab_out d10?0 rssi [2:0] clk2 dvcc enc enc gnd avcc b_sel a_sel analog mux gain gain rssi 3 0db, ?2db, ?4db atten atten 0db, ?2db, ?4db detect peak set rssi ain ain bin bin ad6600
ad6600* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. documentation application notes ? an-302: exploit digital advantages in an ssb receiver ? an-502: designing a superheterodyne receiver using an if sampling diversity chipset ? an-835: understanding high speed adc testing and evaluation ? an-851: a wimax double downconversion if sampling receiver design data sheet ? ad6600: dual channel, gain-ranging adc with rssi data sheet product highlight ? introducing digital up/down converters: versacomm? reconfigurable digital converters reference materials technical articles ? basics of designing a digital radio receiver (radio 101) ? correlating high-speed adc performance to multicarrier 3g requirements ? designing a super-heterodyne multi-channel digital receiver ? digital up/down converters: versacomm? white paper ? dnl and some of its effects on converter performance ? ms-2210: designing power supplies for high speed adc ? smart partitioning eyes 3g basestation design resources ? ad6600 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad6600 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
rev. 0 C2C ad6600?pecifications dc specifications test ad6600ast parameter temp level min typ max unit analog inputs (ain, ain /bin, bin ) differential analog input voltage range 1 full v 2.0 v p-p differential analog input resistance 2 full iv 160 200 240 ? differential analog input capacitance 25 c v 1.5 pf peak detector (internal), rssi resolution 3 bits rssi gain step full v 6 db rssi hysteresis 3 full v 6 db resonant port (flt, flt ) differential port resistance full v 630 ? differential port capacitance full v 1.75 pf a/d converter resolution full iv 11 bits encode inputs (enc, enc ) differential input voltage (ac-coupled) 4 full iv 0.4 v p-p differential input resistance 25 cv 11 k ? differential input capacitance 25 c v 2.5 pf a/b mode inputs (a_sel, b_sel) 5 input high voltage range full iv 4.75 5.25 v input low voltage range full iv 0.0 0.5 v power supply supply voltages avcc full ii 4.75 5.0 5.25 v dvcc full iv 3.0 3.3 5.25 v supply current i avcc (avcc = 5.0 v) full ii 145 182 ma i dvcc (dvcc = 3.3 v) full ii 15 20 ma power consumption 6 full ii 775 976 mw notes 1 analog input range is a function of input frequency. see ac specifications for 70 mhz?50 mhz inputs. 2 analog input impedance is a function of input frequency. see ac specifications for 70 mhz?50 mhz inputs. 3 six db of digital hysteresis is used to eliminate level uncertainty at the rssi threshold points due to noise and amplitude var iations. 4 encode inputs should be ac-coupled and driven differentially. see encoding the ad6600 for details. 5 a_sel and b_sel should be tied directly to ground or avcc. 6 maximum power consumption is computed as maximum current at nominal supplies. specifications subject to change without notice. digital specifications test ad6600ast parameter temp level min typ max unit logic outputs (d10?0, ab_out, rssi2?) 1 logic compatibility cmos logic ??voltage (dvcc = 3.3 v) full ii 2.8 dvcc ?0.2 v logic ??voltage (dvcc = 3.3 v) full ii 0.2 0.5 v logic ??voltage (dvcc = 5.0 v) full iv 4.0 dvcc ?0.35 v logic ??voltage (dvcc = 5.0 v) full iv 0.35 0.5 v output coding (d10?0) two? complement clk2 output 1, 2 logic ??voltage (dvcc = 3.3 v) full ii 2.8 dvcc ?0.2 v logic ??voltage (dvcc = 3.3 v) full ii 0.2 0.5 v logic ??voltage (dvcc = 5.0 v) full iv 4.0 dvcc ?0.3 v logic ??voltage (dvcc = 5.0 v) full iv 0.35 0.5 v notes 1 digital output load is one lcx gate. 2 clk2 output voltage levels, high and low, tested at switching rate of 10 mhz. specifications subject to change without notice. (avcc = 5 v, dvcc = 3.3 v; t min = ?0 c, t max = +85 c unless otherwise noted.) (avcc = 5 v, dvcc = 3.3 v; t min = ?0 c, t max = +85 c unless otherwise noted.)
rev. 0 C3C ad6600 timing requirements and switching specifications 1 (avcc = 5 v, dvcc = 3.3 v; enc and enc = 20 msps; t min = ?0 c, t max = +85 c unless otherwise noted.) test ad6600ast parameter name temp level min typ max unit a/d converter conversion rate f enc 1/(t enc ) msps maximum conversion rate full ii 20 msps minimum conversion rate full iv 6 msps aperture uncertainty t j 25 c v 0.3 ps rms encode inputs (enc, enc ) 2 period t enc full ii 50 ns pulsewidth high 3 t ench full iv 20 ns pulsewidth low 4 t encl full iv 20 ns 2 clock output (clk2 ) 5 output frequency 2 f enc msps output period 6 t clk2 _1 full v t encl ns t clk2 _2 full v t ench ns clk2 pulsewidth low 6 t clk2 l full v t ench /2 ns output risetime 7 full v 3 ns output falltime 7 full v 2.6 ns output rise/fall times 8 output risetime (d10:d0, rssi2:0) full v 8 ns output falltime (d10:d0, rssi2:0) full v 8.4 ns output risetime (ab_out) full v 6 ns output falltime (ab_out) full v 6.2 ns notes 1 see ad6600 timing diagrams. 2 all switching specifications tested by driving enc and enc differentially. 3 several timing specifications are a function of encode high time, t ench ; these specifications are shown in the data tables and timing diagrams. encode duty cycle should be kept as close to 50% as possible. 4 encode pulse low directly affects the amount of settling time available at flt resonant port. see external analog (resonant) fi lter section for details. 5 the 2 clock is generated internally, therefore some specifications are functions of encode period and duty cycle. all timing measure ments to or from clk2 are referenced to 2.0 v crossing. 6 this specification is a function of encode period and duty cycle; reference timing diagrams figure 8. 7 output rise time is measured from 20% point to 80% point of total clk2 voltage swing; output fall time is measured from 80% point to 20% point of total clk2 voltage swing. 8 output rise time is measured from 20% point to 80% point of total data voltage swing; output fall time is measured from 80% poi nt to 20% point of total data voltage swing. all outputs specified with 10 pf load. specifications subject to change without notice.
rev. 0 C4C ad6600?pecifications timing requirements and switching specifications 1, 2 (avcc = 5 v, dvcc = 3.3 v; enc and enc = 20 msps, duty cycle = 50%; t min = ?0 c, t max = +85 c unless otherwise noted.) test ad6600ast parameter name temp level min typ max unit encode/clk2 encode rising to clk2 falling 3 t cf full iv 6.5 8.0 9.5 ns encode rising to clk2 rising 4 t cr full iv t cf + (t ench )/2 ns @ encode = 13 msps, 50% duty cycle full iv 25.7 27.2 28.7 ns @ encode = 20 msps, 50% duty cycle full iv 19.0 20.5 22.0 ns clk2 /data (d10:0, rssi2:0) 5 clk2 to data rising low delay 3 t 2 _drl full iv 3.0 6.5 ns clk2 to data hold time 3 t h_d2 full iv 3.0 6.5 ns clk2 to data falling low 3, 6 t 2 _dfl 25 c iv 10.0 15.0 20.0 ns full iv 11.0 15.5 22.0 ns clk2 to data setup time 4 t s_d2 full iv t ench ?t 2 _dfl ns @ encode = 13 msps, 50% duty cycle full iv 16.5 23.0 ns @ encode = 20 msps, 50% duty cycle 6 25 c iv 5.0 10.0 ns full iv 3.0 9.5 ns clk2 /ab_out 5 clk2 to ab_out rising low delay 3 t 2 _arl full iv 7.0 11.0 ns clk2 to ab_out hold time 3 t h_a2 full iv 7.0 11.0 ns clk2 to ab_out falling low delay 3, 6 t 2 _afl 25 c iv 12.0 18.0 23.0 ns full iv 10.7 19.0 26.0 ns clk2 to ab_out setup time 4 t s_a2 full iv t ench ?t 2 _afl ns @ encode = 13 msps, 50% duty cycle full iv 12.5 19.5 ns @ encode = 20 msps, 50% duty cycle 6 25 c iv 2.0 7.0 ns full iv ?.0 6.0 ns encode/data (d10:0, rssi2:0) encode to data rising low delay 4 t en_drl full iv t cr + t 2 _drl ns encode to data hold time 4 t h_den full iv t en_drl ns @ encode = 13 msps, 50% duty cycle full iv 28.7 33.7 ns @ encode = 20 msps, 50% duty cycle full iv 22.0 27.0 ns encode to data falling low delay 4 t en_dfl full iv t cr + t 2 _dfl ns encode to data delay (setup) 4 t s_den full iv t enc ?t en_dfl ns @ encode = 13 msps, 50% duty cycle full iv 26.2 34.2 ns @ encode = 20 msps, 50% duty cycle 6 25 c iv 8.0 14.5 ns full iv 6.0 14.0 ns encode/ab_out encode to ab_out rising low delay 4 t en_arl full iv t cr + t 2 _arl ns encode to ab_out delay (hold) 4 t h_aen full iv t en_arl ns @ encode = 13 msps, 50% duty cycle full iv 32.7 38.2 ns @ encode = 20 msps, 50% duty cycle full iv 26.0 31.5 ns encode to ab_out falling low delay 4 t en_afl full iv t cr + t 2 _afl ns encode to ab_out delay (setup) 4 t s_aen full iv t enc ?t en_afl ns @ encode = 13 msps, 50% duty cycle full iv 22.2 30.7 ns @ encode = 20 msps, 50% duty cycle 6 25 c iv 5.0 11.5 ns full iv 2.0 10.5 ns notes 1 see ad6600 timing diagrams. 2 all switching specifications tested by driving enc and enc differentially. 3 this specification is not a function of encode period and duty cycle. 4 this specification is a function of encode period and duty cycle. 5 clk2 referenced to 2.0 v crossing; digital output levels referenced to 0.8 v and 2.0 v crossings; all outputs with 10 pf load. 6 for these particular specifications, the 25 c specification is valid from 25 c to 85 c. the full temperature specification includes cold temperature extreme and covers the entire range, ?0 c to +85 c. specifications subject to change without notice.
rev. 0 C5C ad6600 ac specifications test ad6600ast parameter temp level min typ max unit analog inputs 1 analog input 3 db bandwidth 2 full v 450 mhz differential analog input voltage range 70 mhz full v 2.45 v p-p 150 mhz full v 2.57 v p-p 200 mhz full v 2.62 v p-p 250 mhz full v 2.86 v p-p differential analog input impedance 3 70 mhz 25 c v 197?24 ? 150 mhz 25 c v 188?48 ? 200 mhz 25 c v 175?57 ? 250 mhz 25 c v 161?67 ? 300 mhz 25 c v 151?73 ? 350 mhz 25 c v 140?80 ? 400 mhz 25 c v 141?75 ? 450 mhz 25 c v 173?107 ? full-scale input power 70 mhz full v 5.8 dbm 150 mhz full v 6.3 dbm 200 mhz full v 6.7 dbm 250 mhz full v 7.7 dbm full-scale gain tolerance 4 70 mhz?50 mhz full v 0.5 db 200 mhz 5 25 c i ?.0 0.1 +1.0 db gain error ain = 200 mhz @ ?6 dbfs 25 c i ?.5 +1.5 db gain matching (input a:b) 70 mhz?50 mhz full v 0.1 db 200 mhz full ii ?.5 0.05 +0.5 db range-to-range gain tolerance 70 mhz?50 mhz full v 0.1 db range-to-range phase tolerance 70 mhz full v 0.2 degree 250 mhz full v 0.5 degree channel isolation 6 70 mhz?50 mhz full iv 45 50 db noise 7 minimum attenuation level full v 34 v rms maximum attenuation level full v 869 v rms attenuator 3oip 8 full v +33 dbm signal-to-noise ratio (snr) 9, 10, 11 ain = 70 mhz @ ? dbfs 25 civ5559 db @ ? dbfs 25 c v 54.5 db @ ?0 dbfs 25 civ4549 db @ ?2 dbfs to ?2 dbfs 25 c iv 41 48 6db @ ?4 dbfs 25 civ3134 db ain = 150 mhz @ ? dbfs 25 civ5558 db @ ? dbfs 25 cv 54 db @ ?0 dbfs 25 civ4549 db @ ?2 dbfs to ?2 dbfs 25 c iv 41 48 6db @ ?4 dbfs 25 civ3134 db (avcc = 5 v, dvcc = 3.3 v; enc and enc = 20 msps, duty cycle = 50%; t min = ?0 c, t max = +85 c unless otherwise noted.)
rev. 0 C6C ad6600?pecifications ac specifications (continued) test ad6600ast parameter temp level min typ max unit analog inputs (continued) signal-to-noise ratio (continued) ain = 200 mhz @ ? dbfs 25 c i 55 57.5 db @ ? dbfs 25 c v 53.5 db @ ?0 dbfs 25 c i 45 49 db @ ?2 dbfs to ?2 dbfs 25 c i 40.5 48 6db @ ?4 dbfs 25 c i 31 34 db ain = 250 mhz @ ? dbfs 25 civ5256 db @ ? dbfs 25 c v 53.5 db @ ?0 dbfs 25 civ4349 db @ ?2 dbfs to ?2 dbfs 25 c iv 40 48 6db @ ?4 dbfs 25 civ3034 db second harmonic ain = 70 mhz @ ? dbfs full v 69 dbc @ ? dbfs full v 68 dbc @ ?2 dbfs to ?2 dbfs full v 68 6 dbc ain = 150 mhz @ ? dbfs full v 60 dbc @ ? dbfs full v 59 dbc @ ?2 dbfs to ?2 dbfs full v 67 6 dbc ain = 200 mhz 9, 10, 11 @ ? dbfs 25 c i 50 60 dbc @ ? dbfs full v 56 dbc @ ?0 dbfs 25 c i 48 55 dbc @ ?2 dbfs to ?2 dbfs full v 65 6 dbc @ ?4 dbfs full v 50 dbc ain = 250 mhz @ ? dbfs full v 54 dbc @ ? dbfs full v 62 dbc @ ?2 dbfs to ?2 dbfs full v 65 6 dbc third harmonic ain = 70 mhz @ ? dbfs full v 77 dbc @ ? dbfs full v 76 dbc @ ?2 dbfs to ?2 dbfs full v 67 6 dbc ain = 150 mhz @ ? dbfs full v 65 dbc @ ? dbfs full v 70 dbc @ ?2 dbfs to ?2 dbfs full v 66 6 dbc ain = 200 mhz 9, 10, 11 @ ? dbfs 25 c i 50 55 dbc @ ? dbfs full v 58 dbc @ ?0 dbfs 25 c i 55 66 dbc @ ?2 dbfs to ?2 dbfs full v 65 6 dbc @ ?4 dbfs full v 62 dbc ain = 250 mhz @ ? dbfs full v 50 dbc @ ? dbfs full v 56 dbc @ ?2 dbfs to ?2 dbfs full v 65 6 dbc ain = 70 mhz?50 mhz @ ?5 dbfs full iv 28 35 dbc
rev. 0 C7C ad6600 ac specifications (continued) test ad6600ast parameter temp level min typ max unit worst other spur (4th or higher) ain = 70 mhz @ ? dbfs full v 74.5 dbc @ ? dbfs full v 71 dbc @ ?2 dbfs to 42 dbfs full v 68 6 dbc ain = 150 mhz @ ? dbfs full v 67 dbc @ ? dbfs full v 65 dbc @ ?2 dbfs to 42 dbfs full v 67 6 dbc ain = 200 mhz @ ? dbfs 25 c i 60 67 dbc @ ? dbfs full v 66 dbc @ ?0 dbfs 25 c i 55 66 dbc @ ?2 dbfs to 42 dbfs full v 65 6 dbc ain = 250 mhz @ ? dbfs full v 66.5 dbc @ ? dbfs full v 65 dbc @ ?2 dbfs to 42 dbfs full v 65 6 dbc notes 1 ain, ain /bin, bin : the ad6600 analog inputs are unconditionally stable and guarantee proper operation over the 70 mhz?50 mhz specified operating range. circuit board layout is critical on this device, and proper pcb layout must be employed to achieve specified results. 2 analog input 3 db bandwidth is determined by internal track-and-hold. the front-end attenuators have a bandwidth of 1 ghz. 3 measured real and imaginary values using network analyzer. 4 full-scale gain tolerance is the typical variation in gain at a given if input frequency. the nominal value for full-scale inpu t power is a function of frequency as shown in previous specification. 5 full-scale gain tolerance measured at 200 mhz analog input referenced to 6.7 dbm nominal full-scale input power. for the gain me asurement test, the input signal level is set to ? dbfs. tuning port bandwidth is set to 50 mhz. 6 main channel set to full-scale input power. diversity channel swept from ?0 dbfs to ?0 dbfs. 7 measurement includes thermal and quantization noise at 70 mhz analog input. tuning port bandwidth is set to 50 mhz. 8 test tones at 160.05 mhz and 170.05 mhz. 9 measurements at ? dfbs, ? dbfs, and ?0 dbfs are in highest attenuation mode, rssi = 101. 10 each gain-range is checked at ~3 db from rssi trip point (not in hysteresis); nominally ?6 dbfs (rssi = 100), ?2 dbfs (rssi = 01 1), ?8 dbfs (rssi = 010), ?5 dbfs (rssi = 001). 11 measurement at ?4 dbfs is in the lowest attenuation mode, rssi = 000. specifications subject to change without notice.
rev. 0 ad6600 C8C absolute maximum ratings 1 parameter min max unit electrical avcc voltage 0 7 v dvcc voltage 0 7 v analog input voltage 2 0 avcc v analog input current 2 25 ma digital input voltage 3 0 avcc v output current 4 4ma resonant port voltage 5 0 avcc v environmental 6 operating temperature range (ambient) ?0 +85 c maximum junction temperature 150 c lead temperature (soldering, 10 sec) 300 c storage temperature range (ambient) ?5 +150 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 pins ain, ain , bin, bin. 3 pins enc, enc , a_sel, b_sel. 4 pins d10:0, rssi2:0, ab_out, clk2 . 5 pins flt, flt. 6 typical thermal impedance (44-lead lqfp); jc = 16 c/w, ja = 55 c/w. explanation of test levels test level i. 100% production tested. ii. 100% production tested at 25 c and guaranteed by design and characterization at temperature extremes. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. ordering guide temperature package package model range description option ad6600ast ?0 c to 44-terminal lqfp st-44 +85 c (low-profile quad (ambient) plastic flatpack) ad6600st/pcb evaluation board with ad6600ast caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad6600 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recom- mended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. 0 C9C ad6600 pin function descriptions pin number name function 1, 33 dvcc digital vcc for digital outputs. can be 3.3 v. 2, 5, 13, 19, 21, 24, 30, 32 gnd ground. 3 c1 internal bias point. bypass by 0.01 f to gnd. 4, 14, 15, 18, 20, 25, 31 avcc 5 v power supply. 6? rssi[2:0] rssi digital output bits. 9, 10 b_sel, a_sel mode select pins for analog input channel a and b sampling. 11 ain true analog input channel a. 12 ain complementary analog input channel a. 16, 17 flt , flt resonant filter pins for external lc noise filter. 22 bin complementary analog input channel b. 23 bin true analog input channel b. 26 enc complementary encode input. 27 enc true encode input. 28 clk2 2 clock output used for clocking digital filter chips. 29 ab_out digital output flag indicating whether output is input a (high) or b (low). 34 d0 digital data output bit (least significant bit) * . 35?3 d1?9 digital data output bits * . 44 d10 digital data output bit (most significant bit) * . * digital outputs (d10:d0) in two? complement format. pin configuration 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 29 30 31 32 33 27 28 25 26 23 24 pin 1 identifier top view (not to scale) 12 13 14 15 16 17 18 19 20 21 22 dvcc gnd avcc gnd ab_out clk2 enc ad6600 enc avcc gnd bin gnd d10 (msb) d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) avcc gnd bin flt ain gnd avcc avcc flt avcc dvcc gnd c1 avcc gnd rssi2 rssi1 rssi0 b_sel a_sel ain
rev. 0 ad6600 C10C definitions of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. the bandwidth is determined by the internal track-and-hold when the filter node is resonated. aperture delay the delay between the 50% point of the rising edge of the encode command and the instant at which the analog input- is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. attenuator 3oip the third order intercept point of the front end of the ad6600. it is the point at which the third order products would theoreti- cally intercept the input signal level if the input level could increase without bounds. t his is measured using the adc within the ad6600 while the input is stimulated with dual tones in the minimum attenuation (i.e., maximum gain) range. channel isolation the amount of signal leakage from one channel to the next when one channel is driven with a full-scale input, and the other channel is swept from ?0 dbfs to ?0 dbfs with a frequency offset. the leakage is measured on the side with the smaller signal. differential analog input resistance, differential analog input capacitance and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capaci- tance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. the difference is then computed between both peak measurements. differential nonlinearity the deviation of any code width from an ideal 1 lsb step. differential resonant port resistance the resistance shunted across the resonant port (nominally 630 ? ). used to determine the filter bandwidth and gain of that stage. encode pulsewidth/duty cycle pulsewidth high is the minimum amount of time that the encode pulse should be left in logic ??state to achieve rated performance; pulsewidth low is the minimum time encode pulse should be left in low state. see timing implications of changing t ench in text. at a given clock rate, these specifications define an acceptable encode duty cycle. full-scale gain tolerance unit-to-unit variation in full-scale input power. full-scale input power expressed in dbm. computed using the following equation: power v z full scale full scale rms input = ? ? ? ? ? ? ? ? ? ? ? ? 10 0 001 2 log . gain matching (input a:b) variation in full-scale power between a and b inputs. harmonic distortion, 2nd the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. harmonic distortion, 3rd the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal fre- quency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the encode rate at which parametric testing is performed. noise (for any range within the adc) vz noise fs snr signal dbm dbc dbfs = ?? ? ? ? ? ? ? 0 001 10 10 . where: z is the input impedance, fs is the full-scale of the device for the frequency in question, snr is the value for the particular input level, signal is the signal level within the adc reported in db below full scale. this value includes both thermal and quanti- zation noise. range-range gain tolerance the gain error in the rssi attenuator ladder from one range to the next. range-range phase tolerance the phase error in the rssi attenuator ladder from one range to the next. differential resonant port capacitance the capacitance between the two resonant pins. used to deter- mine filter bandwidth and resonant frequency.
rev. 0 ad6600 C11C rssi gain step the input amplitude span between taps of the rssi (received signal strength) attenuator ladder. ideally each stage should span 6 db of input power. rssi hysteresis the amount of movement in the rssi switch points, depending on the direction of approach. hysteresis prevents unnecessary rssi toggling when input signal power is near a threshold. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral compo- nents, excluding the first five harmonics and dc. worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dbc. ad6600 transfer function ain level dbfs 60 24 0 100 0 90 snr db 80 70 60 50 40 30 20 10 54 30 18 6 42 36 12 48 figure 1. snr vs. input power
rev. 0 ad6600 C12C equivalent circuits 100 100 attenuator stage equivalent input r shown only avcc avcc gnd gnd v ref ain ain 4 /8 gain stage buf gain buf figure 2. analog input stage (channel a shown; channel b is equivalent) avcc gnd gnd avcc bias avcc gnd b_sel isel_a isel_b a_sel figure 3. a_sel, b_sel input mode pins dvcc current mirror dvcc current mirror v ref d10 d0 rssi [2:0] 500 figure 4. digital outputs 315 315 avcc gnd avcc gnd avcc gnd from gain stage to t/h external lc filter flt flt figure 5. resonant (lc noise filter) port r1 17k 1/2 r1 17k 1/2 r2 8k 1/2 r2 8k 1/2 avcc encode encode avcc timing circuits avcc figure 6. encode inputs dvcc current mirror dvcc current mirror v ref clk2 ab_out figure 7. clk2 , ab_out outputs
rev. 0 ad6600 C13C ad6600 timing diagrams encode clk2 d [10:0] rssi [2:0] ab_out t clk2 h1 t clk2 h2 t clk2 l t cf2 t clk2 l t cf1 clk2 2 clk2 1 clk2 2 clk2 1 clk2 2 t 2 1_drl t 2 1_arl t ench t encl t enc t clk2 1 t clk2 2 t cr2 t cr1 t 2 1_dfl t 2 1_afl figure 8. encode to clk2 delays and clk2 propagation delays encode clk2 d [10:0] rssi [2:0] ab_out t clk2 h1 t clk2 h2 t clk2 l t cf2 t clk2 l t cf1 clk2 2 clk2 1 clk2 2 clk2 1 clk2 2 t h_d2 t ench t encl t enc t clk2 1 t clk2 2 t cr2 t cr1 t s_d2 t h_d2 t s_d2 t h_a2 t s_a2 t h_a2 t s_a2 figure 9. clk2 setup-and-hold time characteristics encode clk2 d [10:0] rssi [2:0] ab_out t clk2 h1 t clk2 h2 t clk2 l t cf2 t clk2 l t cf1 clk2 2 clk2 1 clk2 2 clk2 1 clk2 2 t ench t encl t enc t clk2 1 t clk2 2 t cr2 t cr1 t en_dfl t en_afl encode encode encode t en_arl t en_drl figure 10. encode to clk2 delays and encode propagation delays
rev. 0 ad6600 C14C encode clk2 d [10:0] rssi [2:0] ab_out t clk2 h1 t clk2 h2 t clk2 l t cf2 t clk2 l t cf1 clk2 2 clk2 1 clk2 2 clk2 1 clk2 2 t ench t encl t enc t clk2 1 t clk2 2 t cr2 t cr1 t s_den t h_den t s_den t h_den t h_aen t s_aen t h_aen t s_aen encode encode encode figure 11. encode setup-and-hold time characteristics clk2 d [10:0] rssi [2:0] ab_out 3 2.6 8 8.4 6.2 6 figure 12. typical output rise and fall times encode clk2 20 30 50 20 30 18 18 8 8 40% figure 13. encode = 20 msps, duty cycle = 40% encode clk2 20 30 50 20 30 8 8 60% 23 23 figure 14. encode = 20 msps, duty cycle = 60%
rev. 0 ad6600 C15C theory of operation the ad6600, dual-channel, gain-ranging adc integrates ana- log if circuitry with high speed data conversion. each analog input stage is a 1 ghz, 0 db to 24 db, phase-compensated step attenuator; the step size in each attenuator is 12 db. both input stages drive an analog multiplex function followed by a 12 db/ 18 db gain amplifier. a simple lc noise filter at the output of the gain amplifier is required to resonate at the desired if. this resonant filter port precedes a wide input bandwidth (450 mhz) track-and-hold followed by an 11-bit analog-to-digital converter (adc). a high speed synchronous peak detector monitors sig- nal strength at both input channels. the peak detector drives rssi circuitry that automatically adjusts attenuation and gain on a clock-by-clock basis. the three rssi indicator bits and the eleven adc bits are available at the output providing an expo nent and mantissa data format. together these integrated compo nents form an if sampling, high dynamic range adc system. it is helpful to view this device as a stand-alone adc using automatic gain control. the gain control referred to in this data sheet as gain-ranging works to maintain a constant snr over as wide a range as possible. as stated previously, the ad6600 has a floating-point output: eleven mantissa bits and three exponent bits. as shown in fig- ure 16, at the lowest input levels snr increases 1 db for a 1 db increase in input power. in this range, the ad6600 is set for maximum gain. however, when the input signal level reaches the gain-ranging section (approximately 42 dbfs), the snr is contained between about 50 db and 56 db or between 44 db and 56 db including the effects of hysteresis. although figure 16 does not indicate so, there are slight differences between the snr from one gain range to the next as the gain amp sw itches between 12 db and 18 db. once the final rssi range has been exceeded (approximately 12 dbfs), snr again increases 1 db per 1 db input power increase until converter full scale is reached. again, this performance is very much like the effects of a typical analog agc loop. gain a/d converter timing encode select gain +12, +18db encode flt flt noise filter resonant port 630 rssi 3 two's complement 11 ab_out d10 d0 rssi [2:0] clk2 dvcc enc enc gnd avcc b_sel a_sel analog mux gain gain rssi 3 0db, 12db, 24db atten atten 0db, 12db, 24db detect peak set rssi ain ain bin bin ad6600 figure 15. functional block diagram snr db 12 48 24 28 ain dbfs 32 36 40 44 48 52 56 60 18 42 54 30 36 60 24 66 72 78 84 90 96 0 90 20 16 12 8 4 0 12db snr window 101 100 011 010 001 000 101 100 011 010 001 000 -,' .!
a = 1 ad6600 subcircuits input step attenuator and gain stage the ad6600 has two identical input attenuators, channel a and channel b. these dual inputs are typically used as diversity channels but may also process two independent if signals. for maximum oversampling the device is used in single channel mode; in this case only one input channel is required. the attenuator steps are 0 db, 12 db and 24 db. the attenuator settings are based on the decisions of the rssi stage (see peak detector/ rssi section). the outputs of the attenuators connect to an analog multiplexer that selects either channel a or b for subse- quent processing (see input mode). the selected signal drives a dual-gain amplifier set to either 12 db or 18 db; the selected gain is also determined by the rssi stage. therefore, based on all possible combinations of attenuation and gain, the input signal receives 12 db to +18 db of voltage gain in 6 db steps (table i). overall gain-matching is typically within 0.1 db. with a bandwidth of 1 ghz, the phase delay through the front-end ranges from 0.2 degrees to 0.5 degrees, depending on input frequency. additionally, the input impedance does not change with attenuator settings so there is no am-to-pm distortion.
rev. 0 ad6600 C16C table i. attenuator and gain settings attenuator gain amp total rssi word 0 db +18 db +18 db 000 0 db +12 db +12 db 001 12 db +18 db +6 db 010 12 db +12 db 0 db 011 24 db +18 db 6 db 100 24 db +12 db 12 db 101 high-speed peak detector and rssi circuitry the peak detector along with the attenuator and dual gain amplifier form the control loop within the ad6600. the peak detector is designed to follow the analog input one clock cycle before the conversion is actually made. therefore, while the converter section of the ad6600 is converting sample n, the peak detector is already looking at sample n+1. while look- ing at the n+1 sample (the calibration period), the peak detec- tor examines the envelope of the input signal. the more of an envelope that is tracked, the more accurate the gain setting. at the very least, the peak detector must be presented either a positive or negative sinusoidal peak, which represents about one-half of a sine wave cycle. since the peak detector works for a complete cycle prior to conversion, the absolute minimum if frequency that can be determined is twice the sample rate per channel. therefore, at 15 msps, the minimum if frequency that can be sampled would be 30 mhz. note that the more cycles of the input that are monitored by the peak detector, the more accurate the gain setting will be. there- fore, the actual minimum if frequency recommended is higher than this. the minimum specified frequency is 70 mhz. since the rssi control loop is performed on a sample-by-sample basis, the ad6600 very accurately follows the signals into and out of a deep fade. hysteresis the ad6600 employs hysteresis to prevent the gain-ranging from unnecessarily changing when the signal envelope is near an rssi threshold. the hysteresis is digital and will acco unt for exactly 6 db of shift, depending on whether the signal is increasing or decreasing. this effect is shown in the dashed lines of the over- all transfer function, figure 16. external lc noise filter, resonant port the output of the attenuator/gain stage drives the wide bandw idth track-and-hold (t/h), followed by the adc encoder. because the attenuator/gain stage has a very wide bandwidth (~1 ghz), an lc filter or resonant port is provided to limit the amount of wideband noise delivered to the adc. the simple lc filter does not provide signal selectivity and should typically be 35 mhz to 50 mhz wide. however, because the adc s track-and-hold itself has a wide bandwidth (~450 mhz), this noise-limiting filter is critical to meeting overall sensitivity. specific details on select- ing components for the resonant port are provided later in the text (understanding the external analog filter). adc encoder after the calibration period is complete (one clock cycle), the appropriate gain and attenuator settings are determined and set. once settled, the internal track-and-hold freezes the input signal so that the adc encoder may digitize the signal. during digiti- zation, the peak detector/rssi circuitry is already looking at the next sample. when the ad6600 is in dual channel mode, the process is interleaved: while channel b is monitored for signal strength, channel a is digitized. this allows the rssi to update on a clock-by-clock basis. digitize old data t-and-h hold t-and-h track adc digitize t-and-h hold rssi cal. rssi set noise filter discharge noise filter settling 4/8 amp clamped noise filter settling encode if input internal 2 clock rssi calibration amplifier control t/h input figure 17. internal timing figure 17 shows the internal timing of the chip. the encode applied to the device initiates several actions. the first and most important is that the track-and-hold is placed in hold, thus sampling the analog input at that instant. the second action is that the peak detector of the rssi circuitry is initialized. during this period, the analog input envelope is monitored to determine signal power. the ad6600 is in calibration mode for about one- quar ter of the encode period. while the ad6600 is in calibration, the external noise filter is discharged and the amplifier driving the filter disabled. since this filter is shared between the two input channels in dual channel mode, this greatly reduces the feedthrough between the chan nels that would otherwise exist. one-quarter of an encode period after the calibration is complete, the amplifier is re-enabled and allowed to settle to its new signal conditions for sampling by the w ideband t/h on the next encode signal. the final action is that the signal on the resonant port is sampled by the track-and-hold. this happens on the next rising edge of the encode. input mode select the ad6600 has two operating modes: single channel and dual channel. in single channel mode, the adc always samples chan- nel a or always samples channel b. in dual channel mode, the adc converter is sampling channel a and channel b on alter- nating encode cycles. two control pins are provided to select the desired mode of operation. a_sel and b_sel arbitrate the selection of how these input channels are connected to the out- put. table ii shows the truth table for selection of the input.
rev. 0 ad6600 C17C table ii. selecting ad6600 operating mode output vs. encode clock mode a_sel b_sel n n+1 n+2 n+3 dual: a/b 1 1 a b a b single: a 1 0 a a a a single: b 0 1 b b b b not valid 00 a_sel and b_sel are not logic inputs and should be tied directly to ground or analog vcc (5 v analog). in dual channel mode, the ab_out signal indicates which input is currently available on the digital output. when the ab_out is 1, the digital output is the digitized version of channel a. likewise, when ab_out is 0, the channel b is available on the digital output (table iii). table iii. ab_out for dual channel operation output data vs. encode clock a_sel and b_sel = 1 n n+1 n+2 n+3 d[10:0], rssi[2:0] a b a b ab_out 1010 data output stage the output stage provides data in the form of mantissa, d[10:0], and exponent, rssi[2:0], where d[10:0] represents the output of the 11-bit adc coded as two s complement, and rssi[2:0] represents the gain-range setting coded in offset binary. table iv shows the nominal gain-ranges for a nominal 2 v p-p differ- ential full-scale input. keep in mind that the actual full-scale input voltage and power will vary with input frequency. table iv. interpreting the rssi bits differential rssi [2:0] analog input voltage decimal attenuation (v p-p) binary equiv. or gain (db) 0.5 < v in 101 5 12 0.25 < v in < 0.5 100 4 6 0.125 < v in < 0.25 011 3 0 0.0625 < v in < 0.125 010 2 +6 0.03125 < v in < 0.0625 001 1 +12 v in < 0.03125 000 0 +18 the digital processing chip which follows the ad6600 can com- bine the 11 bits of two s complement data with the 3 rssi bits to form a 16-bit equivalent output word. table v explains how the rssi data can be interpreted when using a pld or asic. basically, the circuit performs right shifts of the data depending on the rssi word. this can also be performed in software using the following pseudo code fragment: r0 = dm (rssi); r2 = 5; r0 = r2 r0; r1 = dm (adc); (11 bits, msb justified into dsp word) rshift r1, r0; (arithmetic shift to extend the sign bit) the result of the shifted data is a 16-bit fixed-point word that can be used as any normal 16-bit word. table v. 16-bit, fixed-point data format 16-bit data corresponds to a rssi 11-bit word format shift right of 101 data data 32 5 100 data data 16 4 011 data data 83 010 data data 42 001 data data 21 000 data data 10 when mated with the ad6620, digital receive processor chip, the ad6600 floating point data (mantissa + exponent) is automati- cally converted to 16-bit two s complement format by the ad6620. applying the ad6600 encoding the ad6600 the ad6600 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. digitizing high frequency signals (if range 70 mhz 250 mhz) places a premium on encode clock phase noise. snr perfor- mance can easily degrade by 3 db 4 db with 70 mhz input signals when using a high-jitter clock source. at higher ifs (up to 250 mhz), and w ith high-jitter clock sources, the higher slew rates of the input signals reduce performance even further. see an-501, aperture uncertainty and adc system performance for complete details. for optimum performance, the ad6600 must be clocked differ- entially. the encode signal is usually ac-coupled into the enc and enc pins via a transformer or capacitors. these pins are biased internally and require no additional bias. figure 18 shows one preferred method for clocking the ad6600. the sine source (low jitter) is converted from single-ended to differential using an rf transformer. the back-to-back schottky diodes across the transformer secondary limit clock excursions into the ad6600 to approximately 0.8 v p-p differential. this helps prevent the larger voltage swings of the clock from feeding through to other portions of the ad6600, and limits the noise presented to the encode inputs. a crystal clock oscillator can also be used to drive the rf transformer if an appropriate limiting resistor (typically 100 ? ) is placed in the series with the primary. encode encode ad6600 t1 1t 5082 2810 diodes sine source 100 figure 18. transformer-coupled sine source
rev. 0 ad6600 C18C if a low jitter ecl/pecl clock is available, another option is to ac-couple a differential ecl/pecl signal to the encode input pins as shown in figure 19. encode encode ad6600 0.1 f 0.1 f vt vt ecl/ pecl figure 19. ac-coupled ecl/pecl encode driving the analog inputs as with most new high-speed, high dynamic range analog-to-digital converters, the analog input to the ad6600 is differential. differ- ential inputs allow much improvement in performance on-chip as if signals are processed through attenuation and gain stages. most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. there are also benefits at the pcb level. first, differential inputs have high common-mode rejection to stray signals such as ground and power noise. they also provide good rejection to common-mode signals such as local oscillator feedthrough. driving a differential analog input introduces some new chal- lenges. most rf/if amplifiers are single-ended and may not obviously interface to the ad6600. however, using simple techniques, a clean interface is possible. the recommended method to drive the analog input port is shown in figure 20. the ad6600 input is actually designed to match easily to a saw filter such as sawtek 855297. this allows the saw filter to be used in a differential mode, which often improves the operations of a saw filter. using network analyzer data for both the saw filter output and the ad6600 input ports (see data tables for ad6600 s 11 data), a conjugate match can be used for maximum power transfer. often an adequate match can be achieved simply by using a shunt inductor to make the port look real (figure 20). for more details on how to exactly match networks, see rf circuit design by chris bowick, isbn: 0-672-21868-2. saw #1 from mixer output saw #2 ad6600 adc ad6630 figure 20. cascaded saw filters with ad6630 where gain is required, the ad6630 differential, low noise, if gain block is recommended. this amplifier provides 24 db of gain and provides limiting to prevent damage to the saw filter and ad6600. the ad6630 is designed to reside between two saw filters. this low noise device is ideally suited to many applications of the ad6600. for more information on the ad6630, reference the ad6630 data sheet. when general purpose gain blocks are used, matching can easily be achieved using a transformer. most gain blocks are available with 50 ? input and output ports. thus matching to the 200 ? impedance of the ad6600 requires only a 1:4 (impedance ratio) transformer as shown in figure 21. ad6600 adc 50 gain block from mixer output figure 21. transformer-coupled gain block in the rare case that better matching is required, a conjugate match between the amplifier selected and the transformer- coupled analog input can be achieved by placing the matching network between the amplifier and the transformer (figure 22). for more details on matching, see the reference mentioned previously for more details. ad6600 adc 50 gain block from mixer output matching network figure 22. gain block and matching network understanding the external analog filter two primary trade-offs must be made when designing the exter- nal resonant filter. the obvious one is the bandwidth of the filter. the second, not so obvious, trade-off is settling time of the filter nodes. resonant filter bandwidth determines the amount of noise that is limited at the center frequency chosen. if the resonant filter is too wide, little noise improvement is seen. if the resonant filter is too narrow, amplitude variation can be seen due to the toler- ance of filter components. if the narrow filter is off center due to these tolerances (or drift), the 4 /8 signal will fall on the transi- tion band of the filter. an optimum starting point for this filter is approximately 50 mhz. resonant filter settling limits the amount of capacitance of this filter. the output of the 4 /8 amplifier is clamped when the adc is processing its input (encode high time). this prevents the amp output from feeding through to the adc (t/h) and cor- rupting the adc results. but, upon the falling edge of encode, the amp must now come out of clamp and present an accurate signal to the adc t/h. the rc of the external filter deter- mines the settling of the amp. if the amp output does not settle, the adc sees an attenuated signal. so obviously, a narrow bandwidth is desired to improve noise performance; but if the filter is too narrow, the amp will not settle and the adc will see an attenuated signal. figure 23 shows a simplified model of the 4 /8 amplifier. a key point to note is that the resistor values in the collector legs are 315 ? nominal with a tolerance of 20%. the filter perfor- mance is determined by these values in conjunction with the internal parasitic capacitance, board parasitics and the external filter components.
rev. 0 ad6600 C19C 315 315 from gain stage avcc gnd clamp encode flt flt resonant filter port figure 23. 4 /8 amplifier clamp circuitry figure 24 shows why settling is important for this circuit. if the 4 /8 amp does not settle (come out of clamp), the amplitude presented to the adc will be decreased. this results in decreased gain when the filter capacitance is too high. encode resonant filter hold track hold clamped settling figure 24. 4 /8 amplifier settling this explains why the total capacitance allowed for the external filter varies depending on the clock rate (actually encode clock high time). if the encode is 13 msps and the duty cycle is 50%, the allowable settling time is 38.5 ns (1/2 of the encode time). our assumption is that the amp should be allowed to settle to 1/4 lsb in this time period. this has been proven with both simulation and empirical analysis. if the settling is assumed to be an rc circuit, then: t = rc; t = time; n = number of bits vae aa a e e e t t ln t t ln o tt ntt n tt n tt n n =? () ?=? () ?=? = = ? ? ? ? ? ? = () 1 21 1 1 2 1 1 2 1 2 2 / / / / / c t rln ns ln pf total encode = () () = () = 05 8192 38 5 315 8192 13 6 . . . ? in this case, c total includes all parasitics and external capaci- tance. r is nominally 315 ? . the 8192 is (4 2048), which is 1/4 lsb of the converter (11 bits, 2048). so for settling purposes, with 13 msps encode and 50% duty cycle, the maximum allowable capacitance for proper settling is c total = 13.6 pf. as stated above, this c total includes the external capacitors, the board parasitics, and the ad6600 parasitics. the parasitics of the ad6600 (lead, internal bond pad and internal connec- tions) at flt and flt are 1.75 pf 0.35 pf (differential). if the resistors are at maximum value (315 + 20%), the maxi- mum allowable capacitance is c total = 11.3 pf. if the duty cycle is less than 50%, the maximum allowable capacitance is further decreased to allow for settling. power supplies care should be taken when selecting a power source. linear supplies are strongly recommended. switching supplies tend to have radiated components that may be received by the ad 6600. each of the power supply pins should be decoupled as closely to the package as possible using 0.1 f chip capacitors. the ad6600 has separate digital and analog power supply pins. the analog supplies are denoted avcc and the digital supply pins are denoted dvcc. although analog and digital supplies may be tied together, best performance is achieved when the supplies are separate. this is because the fast digital output swings can couple switching current back into the analog sup- plies. note that avcc must be held within 5% of 5 volts; how- ever, the dvcc supply may be varied according to output digital logic family. the ad6600 is specified for dvcc = 3.3 v as this is a common supply for digital asics. output loading care must be taken when designing the data receivers for the ad6600. note from the equivalent circuits shown earlier (see equivalent circuits) that d[10:0] and rssi[2:0] contain a 500 ? output series resistor. to minimize capacitive loading, there should only be one gate on each output pin. extra capaci- tive loading will increase output timing and invalidate timing specifications. clk2 and ab_out do not contain the output series resistors. testing for digital output timing is performed with 10 pf loads. layout information the schematic of the evaluation board (figure 25) represents a typical implementation of the ad6600. a multilayer board is recommended to achieve best results. it is highly recommended that high quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. the pinout of the ad6600 facilitates ease of use in the implementation of high frequency, high resolution design practices. all of the digital outputs are segregated to two sides of the chip, with the inputs on the opposite side for isolation purposes. care should be taken when routing the digital output traces. to prevent coupling through the digital outputs into the analog portion of the ad6600, minimal capacitive loading should be placed on these outputs. it is recommended that a fanout of only one be used for all ad6600 digital outputs. the layout of the analog inputs and the external resonant filter are critical. no digital traces must be routed near, under, or above these portions of the circuit. the transformers used for coupling into the analog inputs must be l ocated as close as possible to the analog inputs of the ad6600. the external reso- nant filter components must be physically close to the filter- input pins, yet separated from the analog inputs.
rev. 0 ad6600 C20C the layout of the encode circuit is equally critical. any noise received on this circuitry will result in corruption in the digitiza- tion process and lower overall performance. the encode clock must be isolated from the digital outputs and the analog inputs. evaluation board the evaluation board for the ad6600 is straightforward, con- taining all required circuitry for evaluating the device. the only external connections required are power supplies, clock and the analog inputs. the evaluation board includes the option for an on-board, clock oscillator for encode. power to the analog supply pins of the ad6600 is connected via the power terminal block (tb1). power for the digital interface is supplied via pin 1 of j201, or the vdd e-hole located adja- cent to j201. the vdd supply can vary between 3.3 v to 5.0 v and sets the level for the output digital data (j201). the j201 connector mates directly with the ad6620 (receive signal processor) evaluation board, part # ad6620s/pcb, allowing complete evaluation of system performance. the two analog inputs are connected via sma connectors ain and bin, which are transformer-coupled to the ad6600 inputs. the transformers have a turns-ratio of 1:4 to match the input resistance of the ad6600 (200 ? ) to 50 ? at the sma connectors. the encode signal may be generated using an on-board crystal oscillator, u100. if an on-board crystal is used, r104 must be removed from the board to prevent loading of the oscillator s output. the on-board oscillator may be replaced by an external encode source via the sma connector labeled encode. if an external source is used, it must be a high quality and very low phase noise source. the high if range of the ad6600 (70 mhz 250 mhz) demands that the encode clock be sufficiently pure to maintain performance. the ad6600 output data is latched using 74lcx574 (u201, u202) latches. the clock for these latches is determined by jumper selection on header j1. the clock can be a delayed ver- sion of the encode clock (clka, clkb), or the clk2 gener- ated by the ad6600. a clock is also distributed with the output data (j201) that is labeled clkx (pin 11, j201). the clk is selected with jumpers on header j1 and can be clka, clkb, or clk2 . the resonant lc filter components (sel2, c2 and c3) are omitted. the user must install proper values based on the if chosen. see understanding the external analog filter section of the data sheet for guidelines on selecting these components. table vi. ad6600st/pcb bill of material item quantity reference description 1 3 ain, bin, encode sma connector 2 14 c1, c102 108, c114, c117 118, ceramic chip capacitor 1206, 0.1 f c120 121, c299 3 2 c100 101 tantalum chip capacitor, 10 f 4 1 c111 ceramic chip capacitor 0805, 0.1 f 54c112 c113, c115 116 ceramic chip capacitor 0508, 0.1 f 6 2 cr1 2 1n2810 schottky diode 7 1 dut ad6600ast 8 1 j1 20-pin double row male header 9 1 j201 50-pin double row male header, right angle 10 2 r1 2 omitted 11 2 r100 r101 surface mount resistor 1206, 10 k ? 12 1 r103 surface mount resistor 1206, 100 ? 13 1 r104 surface mount resistor 1206, 50 ? 14 2 r298 r299 surface mount resistor 1206, 2 k ? 15 3 t1 t2, t4 surface mount transformer mini-circuits t4 1t 16 1 tb1 pctb2 terminal block 17 2 u201 u202 74lcx574 octal latch 18 1 u204 74lvq00 two input nand gate
rev. 0 ad6600 C21C ad6600ast 29 30 31 32 33 27 28 25 26 23 24 dvcc gnd avcc gnd ab_out clk2x enc enc avcc gnd bin 3 4 5 6 7 1 2 10 11 8 9 dvcc gnd c1 avcc gnd rssi2 rssi1 rssi0 b_sel a_sel ain 40 39 38 41 42 43 44 36 35 34 37 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (msb) (lsb) 12 13 14 15 16 17 18 19 20 21 22 gnd avcc gnd flt gnd avcc avcc flt avcc ain bin vdd gnd vcc gnd b a c111 0.1 f c112 0.01 f sma ain 4 6 3 1 2 c115 0.01 f sel2 c3 sel c2 sel vcc gnd vcc vcc vcc gnd vcc gnd sma bin 4 6 3 1 2 c116 0.01 f vdd gnd vcc gnd vcc gnd sma encode 4 6 3 1 2 c113 0.01 f c1 0.1 f r1 r2 cr1 1n2810 cr2 1n2810 c114 0.1 f clkref r104 50 r103 100 out v cc vee vcc u100 14 7 8 k1115 2 clk clk_2 8d 8q 7d 7q 6d 6q 5d 5q 4d 4q 3d 3q 2d 2q 1d 1q ck oe 12 13 14 15 16 17 18 19 a/b bit0 bit1 bit2 bit3 bit4 bit5 bit6 11 1 clk u201 74lcx574 8d 8q 7d 7q 6d 6q 5d 5q 4d 4q 3d 3q 2d 2q 1d 1q ck oe 12 13 14 15 16 17 18 19 bit7 bit8 bit9 bit10 rssib2 rssib1 rssib0 11 1 u202 74lcx574 9 8 7 6 5 4 3 2 9 8 7 6 5 4 3 2 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 rssi0 rssi1 rssi2 a/b a/b d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 rssi2 rssi1 rssi0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 h20dm j1 a b clk clka clk_2x clkb gnd gnd clka clkb clkx 50 1 249 348 447 546 645 744 843 942 10 41 11 40 12 39 13 38 14 37 15 36 16 35 17 34 18 33 19 32 20 31 21 30 22 29 23 28 24 27 25 26 h50dm j201 v dd bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 clk clkx bit2 bit1 bit0 gnd gnd gnd gnd gnd gnd gnd rssib2 rssib1 rssib0 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd a/b gnd r100 10k a vcc r101 10k b vcc 1 2 3 r298 2 r299 2k v dd c299 0.1 f clkref u204 74lvq00 9 10 8 u204 74lvq00 gnd gnd 12 13 11 u204 74lvq00 gnd gnd 4 5 6 u204 74lvq00 clka 1 2 tb1 pctb2 + c100 c102 c104 c106 c108 c120 c121 vcc + c101 c103 c105 c107 c117 c118 vdd 1:4 t4 ti 4t ti 4t 1:4 t2 t1 4t 1:4 gnd remove 21 and 30 t1 figure 25. ad6600st/pcb schematic diagram
rev. 0 ad6600 C22C figure 27. ad6600st/pcb top side copper figure 28. ad6600st/pcb bottom side copper figure 29. ad6600st/pcb power supply layer (negative) figure 30. ad6600st/pcb ground layer (negative) figure 26. ad6600st/pcb top side silk screen
rev. 0 ad6600 C23C connecting the ad6600 with the ad6620 the ad6600 interfaces directly to the ad6620 digital receive signal processor as shown in figure 31. no additional external components are required. note that the layout requirements dis- cussed previously do apply and deviations can result in degraded performance. the digital outputs of the ad6600 must connect directly to the ad6620 inputs with no additional fanout. addi- tional loading on the outputs will compromise timing performance. ad6600 ad6620 (msb) d10 d3 d2 d1 (lsb) d0 d9 d8 d7 d6 d5 d4 in15 in14 in13 in12 in11 in10 in9 in8 in7 in6 in5 in4 in3 in2 in1 in0 exp2 exp1 exp0 a/b clk rssi2 rssi1 rssi0 ab_out clk2 enc enc figure 31. ad6600/ad6620 connections figure 32 shows the timing details between the ad6600 and the ad6620. on clock 1, d[10:0], rssi[2:0], and ab_out are captured by the ad6620. since ab_out has changed state from the previous clock, the d[10:0] and rssi[2:0] are processed by the ad6620. this clock allows adequate setup and hold time for ab_out, d[10:0], and rssi[2:0] to be captured by the ad6620. on clock2, d[10:0], rssi[2:0], and ab_out are captured by the ad6620. since ab_out has not changed from the previous clock, the d[10:0] and rssi[2:0] are ignored by the ad6620. this clock is concerned only with the ab_out setup- and-hold time. clk2 d [10:0] rssi [2:0] ab_out 38.5 38.5 3.0 16.5 7.0 3.0 16.5 12.5 clock1 clock2 figure 32. ad6600 to ad6620 timing at 13 msps
rev. 0 ad6600 C24C c00966C2.5C7/00 (rev. 0) printed in u.s.a. 44-terminal lqfp (low-profile quad plastic flatpack) (st-44) top view (pins down) 1 33 34 44 11 12 23 22 0.018 (0.45) 0.012 (0.30) 0.031 (0.80) bsc 0.394 (10.0) sq 0.472 (12.00) sq 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) 0.002 (0.05) seating plane 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) outline dimensions dimensions shown in inches and (mm).

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